1. Field of the Invention
The disclosure relates to an interconnection filed and, more particularly, to a Peripheral Component Interconnect Express in the interconnection filed.
2. Description of the Related Art
In general, computer systems include a number of elements and components. These elements are coupled via a bus or other interconnection ways, such as by the multi-drop parallel bus architecture of the Peripheral Component Interconnect (PCI). Recently, a new generation of I/O bus is used to couple elements, such as a peripheral component interconnect express (PCIE), which makes the transmission among the serial physical layer protocol devices faster.
In the computer system, multiple downstream devices may share a data bus simultaneously, such as LAN, therefore it needs an arbitration mechanism to control the data flow on the bus and determine which downstream device is allowed to access and transmit data. The arbitration architecture often involves two trade-off factors which are fairness and efficiency. However, the arbitration architecture can ensure the fairness but makes the use of bus inefficiently.
If some downstream devices must complete the data transmission within a certain period an entirely fair arbitration mechanism may not allocate the bus access right in time such that the downstream device may occur a deadlock due to errors generating at the transmission. On the other hand, if some of the downstream devices unreasonably occupy bandwidth for a long time, the smoothness in transmitting packets of the entire computer system is affected.